The invention relates generally to improving the performance of an asymmetric multiprocessor (AMP) system.
Most prior multiprocessors are symmetric systems containing plural processors all having identical characteristics.
An asymmetric multiprocessor system is composed of two or more processors which have distinctly different performance characteristics resulting in different performance rates, including a major processor with a greater capability and a minor processor with a lesser capability. The reason why asymmetric processors may be used is because a minor processor may be built with a much better cost/performance ratio than a major processor, when the minor processor is designed to directly execute only a subset of the system instructions directly executable by the major processor. A system instruction set is used by all programs dispatched in the system on either the major or minor processor. Thus many internal differences may exist between the different types of processors in an AMP including differing speeds of execution (usually quantified in MIPS, millions of instructions per second), and different efficiencies in executing the different system instructions. In an AMP, a major processor may have a complete internal native instruction set implemented in hardware/horizontal microcode which directly executes the system instruction set, including variable field-length operations and floating point operations. The minor processor may have a less comprehensive internal hardware/horizontal microcode instruction set (native instructions) which can directly execute only a subset of the system instructions directly executable by the native instructions in the major processor. However with some loss in performance, the addition of vertical microcode for the minor processor provides it with the capability of executing the complete system instruction set by using emulation (e.g. by vertical microcode) for those system instructions not directly executable by the minor processor. Emulation by vertical microcode is accomplished by stored program routines consisting of minor processor native instructions that execute on the minor processor to perform those system instructions which are unavailable in the native instruction set of the minor processor. Hence, a plurality of native instruction executions may be required on the minor processor to emulate one system instruction. With a preferred type of minor processor, many (but not all) of its native instructions will be system instructions which therefore will not require emulation. Other types of minor processors may require emulation of all system instructions, because none of their native instructions will match any system instruction. Consequently, the relative efficiencies of the major and minor processors of an AMP will depend on the relative processor designs and on the instruction mix in programs being executed.
All processors in an AMP generally will be simultaneously executing their own independent tasks. In any multiprocessor system, tasks are assigned to each processor for execution according to a dispatching algorithm which attempts to keep all processors busy in the MP.
Processing of a task is likely to be interrupted by various events, such as interrupts caused by input/output devices. At the time of an interrupt, software mechanisms save all information for a task necessary to resume work at a future time. Upon resumption of execution of an interrupted task, there is no certainty in a multiprocessor system that the same processor will resume work on the interrupted task. Thus, on multiple dispatches of a task, the task may have used differing amounts of CPU time on different processors.
In the prior art, precise accounting is done to obtain the execution time on each processor for each task.
Prior symmetric multiprocessor systems have multiple processors with identical capabilities. Therefore, a task can be dispatched to any available processor in the system, and the task time will be equally well accounted for in any processor. That is to say, a microsecond of CPU time in any of the processors can be said to have equal processing value.
Also in a symmetric system, arbitrary selection among the processors for each next dispatch of any task does not present any system efficiency problem, since any processor in a symmetric system can equally well execute any task.